A liquid crystal display device, for example, includes a TFT substrate on which a plurality of TFTs (thin film transistors) and pixel electrodes connected to the TFTs are arranged in a matrix, an opposite substrate facing the TFT substrate and having a color filter, a common electrode, and the like formed thereon, and a liquid crystal layer provided between the opposite substrate and the TFT substrate.
Here, configuration of a TFT substrate 100 is described with reference to FIG. 10, which is an enlarged cross-sectional view. Over a glass substrate 101 that constitute the TFT substrate 100, a lower layer gate electrode 102, a base coat layer 103, a semiconductor layer 104, and a gate insulating film 105 are layered. On the gate insulating film 105, an upper layer gate electrode 106, which is made of a metal material, is formed. The upper layer gate electrode 106 is covered by a first interlayer insulating film 107 and a second interlayer insulating film 108. On the surface of the second interlayer insulating film 108, a lower layer gate wiring 109, an upper layer gate wiring 110, and a drain wiring 111 are formed.
In recent years, development of so-called system liquid crystal, in which driver circuit and the like are directly formed on the glass substrate that constitute a TFT substrate, has been underway for higher functionality and further refinement of liquid crystal display devices. Furthermore, size reduction (narrowing) of the frame region, which is a non-display region surrounding the display region, is also being sought. However, size reduction of wiring layers such as source wiring is more difficult than the case of semiconductor layers or insulating films.
As a result, as shown in FIG. 10, in a region where the upper layer gate electrode 106, which has a large thickness, is formed, the surface of the second interlayer insulating film 108 significantly rises and results in a level difference. Consequently, when the upper layer gate wiring 110 and the like are patterned by photolithography, the patterning precision is inevitably lowered, possibly causing leakage defects or wire breakage in the wiring layer. For example, as shown in FIG. 10 and FIG. 11, in the corner surrounding the raised portion of the second interlayer insulating film 108, unnecessary wiring layer is difficult to remove completely, and therefore residue 112 can remain. The residue 112 can trigger leakage defects between wirings. FIG. 11 is a photograph showing an enlarged view of the residue 112 formed on the second interlayer insulating film 108.
In a known technique to solve this problem, the substrate surface is planarized using an SOG (spin on glass) film. The SOG film, however, is prone to absorb moisture. Therefore, if, in FIG. 10, an SOG film is formed on the second interlayer insulating film 108, and a wiring layer is formed directly in the contact hole that passes through the SOG film, there occurs a problem that the wiring layer can be oxidized by the SOG film, which contains moisture.
On the other hand, Patent Document 1 discloses that a PTEOS-NSG film, which is an oxidation resistant film, is applied on the inner surface of a via hole formed in the SOG film. That is, first, a lower section wiring layer 116, a PTEOS-NSG film 117, an SOG film 118, and a PTEOS-NSG film 119 are layered over a base insulating film 115 in this order (see FIG. 12). Then, a contact hole 120 is formed in the layered body to expose the PTEOS-NSG film 117. Next, a PTEOS-NSG film 121 is formed to cover the SOG film 118 and the PTEOS-NSG film 119, which are exposed inside the contact hole 120. Then, a contact hole 122 is formed in the PTEOS-NSG film 117 to expose the lower section wiring layer 116. Subsequently, an upper section wiring layer 123 is formed on the surface of the PTEOS-NSG film 119 and inside the contact hole 122 to electrically connect the upper section wiring layer 123 and the lower section wiring layer 116 together.
With this configuration, the PTEOS-NSG film 121 is interposed between the SOG film 118 and the upper section wiring layer 123 to prevent oxidation of the upper section wiring layer 123 by the SOG film 118.